(1) FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuits, and more particularly to a method for fabricating an array of dynamic random access memory (DRAM) cells with Y-shaped stacked capacitors to increase the capacitance while maintaining a high density of memory cells.
(2) DESCRIPTION OF THE PRIOR ART
Dynamic random access memory (DRAM) circuits (devices) are used extensively in the electronics industry, and more particularly in the computer industry for storing data in binary form (1 and 0) as charge on a storage capacitor. These DRAM devices are made on semiconductor substrates (or wafers) and then the substrates are diced to form the individual DRAM circuits (or chips). Each DRAM circuit (chip) consists in part of an array of individual memory cells that store binary data (bits) as electrical charge on the storage capacitors. Further, the information is stored and retrieved from the storage capacitors by means of switching on or off a single access transistor (via word lines) in each memory cell using peripheral address circuits, while the charge stored on the capacitors is sensed via bit lines and by read/write circuits formed on the peripheral circuits of the DRAM chip.
The access transistor for the DRAM device is usually a field effect transistor (FET), and the single capacitor in each cell is either formed in the semiconductor substrate as a trench capacitor, or is built over the FET in the cell area as a stacked capacitor. To maintain a reasonable DRAM chip size and improved circuit performance, it is necessary to further reduce the area occupied by the individual cells on the DRAM chip. Unfortunately, as the cell size decreases, it becomes increasing more difficult to fabricate stacked or trench storage capacitors with sufficient capacitance to store the necessary charge to provide an acceptable signal-to-noise level for the read circuits (sense amplifiers) to detect. The reduced charge also requires more frequent refresh cycles that periodically restore the charge on these volatile storage cells. This increase in refresh cycles further reduces the performance (speed) of the DRAM circuit.
Since the capacitor area is limited to the cell size in order to accommodate the multitude of cells on the DRAM chip, it is necessary to explore alternative methods for increasing the capacitance without increasing the lateral area that the capacitor occupies on the substrate surface. In recent years the method of choice is to build stacked capacitors over the access transistors within each cell area, rather than forming trench capacitors that need to be etched to increasing depths in the substrate to maintain the necessary capacitance. The stacked capacitors also provide increased latitude in capacitor design and processing while reducing cell area. More specifically, the stacked capacitors can be extended in the vertical direction (third dimension) to increase the stacked capacitor area, and therefore to increase the capacitance.
Numerous methods of making DRAM circuits using stacked capacitors have been reported in the literature. One method of making multi-fin stacked capacitors having increased capacitance is described by Hsue et al., U.S. Pat. No. 5,716,884. The method uses alternating layers of two different insulating materials that are used as a template to form multi-fin polysilicon capacitors over the gate electrodes and the field oxide areas for capacitor-under-bit line (CUB) DRAMs. Another approach for making CUB multi-fin stacked capacitors is described by Chang, U.S. Pat. No. 5,567,639, in which the multi-fins are formed over the gate electrodes (word lines) and over the field oxide. Still another approach is taught by Rostoker in U.S. Pat. No. 5,688,709, in which a composite trench-fin capacitor is formed to increase capacitance. The trench is etched in the node contact area, and the fin-shaped portion of the capacitor is formed over the gate electrodes and over the field oxide areas for a CUB DRAM. Ema, U.S. Pat. No. 5,705,420, forms a Y-shaped multi-fin capacitor over the word lines to increase the capacitance on a CUB DRAM device.
Although there has been considerable work done to increase the capacitance area on these miniature stacked capacitors, it is still desirable to further improve on these capacitors while maintaining a simple process to minimize the number of masking steps.